1. Field of Invention
The present invention relates to an isolated device and a manufacturing method of an isolated device; particularly, it relates to such isolated device and manufacturing method wherein the breakdown voltage of the isolated device is increased by suppressing the tunneling effect.
2. Description of Related Art
FIG. 1 shows a cross-section view of a prior art isolated P-type metal oxide semiconductor (PMOS) device 1. As shown in the figure, the isolated PMOS device 1 is formed in a P-type substrate 11, which includes field oxide regions 12. The isolated PMOS device 1 includes a gate 13, an N-type well 14, a P-type drain 15, a P-type source 16, a well contact 17, and a P-type drift-drain region 18. The P-type drain 15, the source 16, and the drift-drain region 18 are formed by a lithography process and an ion implantation process, wherein the lithography process defines the implantation regions by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process implants P-type impurities to the defined regions in the form of accelerated ions. The N-type well 14 and the well contact 17 are respectively formed by lithography processes and ion implantation processes, wherein the ion implantation processes implant N-type impurities to the defined regions in the form of accelerated ions.
If the isolated PMOS device 1 as shown in FIG. 1 is required to be integrated with a high voltage device in one substrate, the high voltage device and the isolated PMOS device 1 should adopt the same manufacturing process steps with the same ion implantation parameters, and thus the flexibility of the ion implantation parameters for the isolated PMOS device 1 is limited; as a result, the isolated PMOS device 1 will have a lower breakdown voltage and therefore a limited application range. Besides, as shown in FIG. 1, the isolated PMOS device 1 includes the N-type well 14 between the P-type substrate 11 and the P-type drift-drain region 18 and thus the tunneling effect between the substrate 11 and the drift-drain region 18 further reduces the breakdown voltage. To mitigate the tunneling effect of the isolated PMOS device 1, one possible solution is to increase the N-type impurity density of the N-type well 14, but this will decrease the breakdown voltage of the high voltage device. To mitigate the tunneling effect without sacrificing the breakdown voltage of the high voltage device, additional manufacturing process steps are required, that is, an additional lithography process and an additional ion implantation process is required in order to provide different ion implantation parameters, or else the area of the high voltage device should be increased, but either way increases the cost.
In view of above, to overcome the drawback in the prior art, the present invention proposes an isolated device and a manufacturing method thereof which provide a higher breakdown voltage so that the protected device may have a broader application range, in which additional manufacturing process steps are not required and the device area is not increased, such that the protected device can be integrated with a high voltage device and manufactured by common manufacturing process steps.